Timeloop/Accelergy Tutorial @ ISCA 2020
May 26, 2020
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1:55:43Now PlayingTimeloop/Accelergy Tutorial @ ISCA 2020
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YouTube Description
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Video of handson exercises can be found at
Outline:
Timeloop Slides
Accelergy Slides
Deep neural networks have emerged as the key approach for solving a wide range of complex problems. To provide high performance and energy efficiency to this class of computation and memory-intensive applications, many DNN accelerators have been proposed in recent years. In order to systematically evaluate arbitrary DNN accelerator designs, we need to have an infrastructure that is able to:
* Describe a wide range of architectures
* Find optimal mappings for a wide range of workloads onto the architecture
* Accurately predict energy for a range of accelerator designs
* Handle a wide range of technologies
In this tutorial, we will present two integrated tools that enable rapid evaluation of DNN accelerators:
* Mapping exploration with Timeloop
* Energy estimation with Accelergy
Tutorial Organizers: Angshuman Parashar (NVIDIA), Yannan Nellie Wu (MIT), Po-An Tsai (NVIDIA), Vivienne Sze (MIT), Joel S. Emer (NVIDIA, MIT)
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